In a semiconductor integrated circuit containing multiple wiring layers, a via is used to connect a wiring of one wiring layer with a wiring of another wiring layer. Generally, for signal lines other than the power lines, one via is provided for each connection point. Such via is called a “single-cut via”.
With the increased miniaturization of a semiconductor integrated circuit, the wiring width has been reduced, and also the cross-sectional area of a via has decreased. Accordingly, in the manufacturing process, it has become difficult to form a via of a desired pattern. In a worst case scenario, an open failure occurs in the single-cut via formation part and thus the desired device operation cannot be implemented, resulting in a lower yield. Further, as the cross-sectional area of a via decreases, the delay time in signal lines increases, and disconnection rate also increases due to electronic migration. These cause lowering of device operation reliability.
In order to address these problems, multiple vias may be provided in parallel for each connection point. Such via is called a “multi-cut via”. Particularly, when two vias are provided for each connection point, such via is called a “double-cut via”. After the wiring layout, when as many single-cut vias as possible are replaced with multi-cut vias, the device operation reliability improves. This related art has been described in US Patent Application Publication Nos. US2005/0280159A1 and US2006/0101367A1.
FIG. 1A is a view illustrating an exemplary wiring layout using a conventional single-cut via. Wirings are laid out along wiring grids T1 to T5. For example, a first wiring W1 extending in a Y direction is laid out along the wiring grid. T5; a second wiring W2 extending in an X direction is laid out along the wiring grid T2. The wirings W1 and W2 lie on different layers, and are connected to each other at an intersection is of the wiring grids T2 and T5. Accordingly, a single-cut via pattern SV is arranged at the intersection IS.
FIG. 1B shows a layer structure of the single-cut via pattern SV. The single-cut via pattern SV is a combination of three figures A1 to A3. The figure A1 is a figure on the same wiring layer as the first wiring W1 and constitutes part of the first wiring W1. On the other hand, the second figure A2 is a figure on the same wiring layer as the second wiring W2 and constitutes part of the second wiring W2. The figure A3 represents a via. The single-cut via pattern SV is arranged so that the center of the figure A3 is located at the center of the intersection IS.
In view of “grid dislocation” occurring during manufacturing of the via, the both ends of the figure A1 are made to protrude by a width OH from the figure A3. Similarly, the both ends of the figure A2 are also made to protrude by a width OH from the figure A3. This width OH is called an “overhang” or “extension”. That is, the overhang OH is provided as design constraint to ensure manufacturing reliability. According to our study, it is confirmed that overhang OH provided at least one of the first wiring W1 direction or the second wiring W2 direction is effective. Particularly, according to the technology where the gate length of a transistor is 90 nm or less, the overhang OH must be set.
FIG. 2A is a view illustrating an exemplary wiring layout using a conventional multi-cut via. Referring to FIG. 2A, instead of a single-cut via pattern SV, a multi-cut via pattern (double-cut via pattern) DV is provided at an intersection of the first wiring W1 and second wiring W2.
The multi-cut via pattern DV is a combination of four figures B1, B2, Ba and Bb. FIG. 2B shows a layer structure of the multi-cut via pattern DV. The figure B1 is a figure on the same layer as the first wiring W1 and constitutes part of the first wiring W1. On the other hand, the figure B2 is a figure on the same layer as the second wiring W2 and constitutes part of the second wiring W2. The figures Ba and Bb represent two vias constituting the multi-cut via. The center of the figure Ba agrees with the center of an intersection ISa of the wiring grids T3 and T5; and the center of the figure Bb agrees with the center of an intersection ISb of the wiring grids T2 and T5.
In the multi-cut via pattern DV, also, similarly to the single-cut via pattern SV, an overhang OH is provided as design constraint. More specifically, the both ends of the figure B1 protrude by the overhang OH from the figures Ba and Bb. Similarly, the both ends of the figure B2 also protrude by the overhang OH from the figures Ba and Bb.
The present inventor has noted the following point. That is, as described above, when a single-cut via is replaced with a multi-cut via, operation reliability improves. However; as the degree of semiconductor integrated circuit integration increases, the wiring becomes more complex. As a result, there is increased probability that the wirings are in close proximity to the vias. And while the overhang OH is set, the gap between wiring grids has become narrow. Thus, it is difficult to replace a single-cut via with a multi-cut via. For example, referring to FIG. 2A, after a wiring has been arranged along the wiring grid T4, a multi-cut via pattern DV cannot be arranged. In this state, if a multi-cut via pattern DV is arranged, there occurs a design violation between the wiring on the wiring grid T4 and the multi-cut via pattern DV. Consequently, not the multi-cut via pattern DV but the single-cut via pattern SV illustrated in FIG. 1A is arranged. Thus, the improvement in operation reliability cannot be expected so much.